DP/ eDP > MHL/HDMI Bridge

Part Number:EP9361(K)

Overview

EP9361(K) is a Display Port/MHL/HDMI Switcher which accepts Display Port (DP) or MHL or HDMI inputs and convert the input signalling to HDMI output. The chip supports 1 DP input port, 1 MHL/HDMI input port and 1 HDMI output port. The DP input port supports 2-lane DP receiving and HDCP decryption. The MHL/HDMI input port supports MHL/HDMI auto detection and HDCP decryption. The HDMI output port supports HDCP encryption. The chip is compliant with Display Port 1.1a, HDCP 1.4, MHL 1.0 and HDMI 1.4a specifications. The chip supports 8/10-bit video upto 1080p 60 Hz for Display Port input, 8-bit video upto 1080i/720p 60 Hz or 8-bit 1080p 30 Hz for MHL input and 12-bit video upto 1080p 60 Hz for HDMI input. The chip also supports Instant Port Switching (IPS) for input port switching between DP and MHL/HDMI.


Feature

•Support 1 DP input port, 1 MHL/HDMI input port and 1 HDMI output port.
•Display Port Specification 1.1a Compliant
•HDCP Specification 1.4 Compliant
•MHL Specification 2.0 Compliant
•HDMI Specification 1.4b Compliant
•Support 1 or 2-lane Display Port receiving
•Support HDCP decryption for DP input
•Support HDCP decryption for MHL/HDMI input
•Support HDCP encryption for HDMI output
•Support MHL/HDMI auto detection on MHL/HDMI input port
•Integrated on-chip HDCP Keys (available for EP9361K)
•Support 8/10-bit video upto 1080p 60 Hz for DP input
•Support up to 75 Mhz Pixel clock rate (8-bit 1080i/720p 60 Hz or 8-bit 1080p 30 Hz) for MHL input
•Support up to 225 Mhz TMDS clock rate (12-bit 1080p 60 Hz) for HDMI input
•Support LPCM and compressed surround audio for DP input
•Support LPCM, compressed surround audio, HBR and DSD audio for MHL/HDMI input
•Integrated EDID memory for both DP and MHL/HDMI input ports
•Register-programmable via slave IIC interface
•3.3V and 1.8V power required
•Support Power Down mode and low stand-by current (< 1mA)
•80-Pin LQFP (10mm x 10mm)