EP124C is a supper high speed 10-bit LVDS 2-port to 4-port bridge with Line Buffer. The chip converts 2-port LVDS input to 4-port LVDS output at a pixel rate of 330 Mhz. With the Line Buffer, the chip can convert data sequence from Even/Odd to Left/Right. The chip is capable of receiving dual-port 10-bit LVDS input at 165 Mhz clock rate per port and convert it to 4-port 10-bit LVDS output at half the input clock rate. The chip adopts Explore’s proprietary eLVDS (Enhanced LVDS) technology which has the advantages of supper high speed and low power characteristics over the conventional LVDS technology.
EP124C supports LVDS transmission for flat panel display up to 1080p double frame rate (120 Hz) by using only 2 ports of LVDS cable/connectors. This will simplify system connectivity and save system cost.
•Supports dual Port 10-bit LVDS input at 330 Mhz pixel rate
•Supports 4-port 10-bit LVDS output at half of input clock rate
•Supports 2-port 10-bit LVDS output at the same clock rate as input
•Supports output data sequence in Sequential Mode and Left/Right Mode
•Supports up to 2048 pixels Line Buffer size
•Supports TV Display resolution up to 1080p double frame rate (120 Hz)
•Supports inter-chip synchronization which provides a solution for 4-port to 8-ports LVDS bridge at a pixel rate of 660 Mhz by using 2 EP124C chips.
•Wide channel skew tolerance: 1/3 bit time
•Supports auto data alignment between ports
•Supports various port swapping scheme
•Supports Power Down Mode
•Power Supply: 3.3V (I/O), 1.8V (core)
•128-pin LQFP (Pb-free)