EP105 is a supper high speed 10-bit LVDS (Low Voltage Differential Signal) transmitter capable of transmitting LVDS outputs at 150 Mhz clock rate. The chip adopts Explore’s proprietary eLVDS (Enhanced LVDS) technology which was developed for supper high speed LVDS interface.
EP105 along with EP106 (eLVDS receiver) support single link transmission between the host and the flat panel display up to 1080p resolution. The chip converts 32 bits (10-bits/color, 2 dummy bits) of CMOS/TTL data and 3 control bits into 5 LVDS data streams. At the maximum input clock rate of 150MHz, each LVDS differential data pair speed is 1.05 Gbps, providing a total throughput of 5.25 Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin.
• Support 8MHz to 150MHz clock rates from NTSC to 1080p resolution
• Up to 5.25Gbps bandwidth
• PLL requires no external components
• Cycle-to-cycle jitter rejection
• Programmable data and control strobe select
• Reduced swing LVDS supported
• Power down mode supported
• Pin-out Compatible with Explore EP103
• Single 3.3V CMOS design
• 64-pin LQFP